Master Thesis: Diagnostic Framework for DMA Engine IP Pipeline Stalls and Performance Regression

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About this opportunity:

High-performance DMA engines move large data between on-chip memory, external memories, and interconnected resources, offloading transfers from DSPs and CPUs. Because data and control paths are deep and tightly coupled, performance loss is hard to localize. Pipeline stalls (bubbles) can stem from arbitration delays, backpressure, or credit exhaustion; the observed throughput drop alone doesn't reveal why. Typical UVM-based performance environments quantify behavior - sweeping DMA size, queue loading, traffic patterns, and interface latency - to flag below-expectation operating points, but they don't explain root cause. Today, closing this gap means digging into waveforms and manually correlating throughput loss to specific stall events, conditions, and stages - a time-consuming process that's often inconclusive given pipeline depth and concurrency.

In this thesis, you will build a diagnostic observability layer that plugs into the existing UVM performance environment and turns each sub-par point on a performance curve into a localized, actionable root-cause explanation. The layer should automatically capture where stalls occur, under which conditions, and from which internal or external source - making performance debugging early, repeatable, and conclusive instead of a manual end-stage effort. A secondary track can extend this to dataset design for AI-parseable stall analysis.



What you will do:

The assignment of this thesis is twofold. The first goal is to establish a custom dynamic stall identification (runtime/observability) framework:

• Instrument the DMA Engine pipeline within the existing UVM performance environment with non-intrusive monitors capturing per-stage handshake activity, occupancy, and stall conditions.
• Define a precise, measurable notion of a stall relative to the saturated reference case.
• Produce a time-stamped, structured dataset (CSV/Parquet) of stall events tagged with stage, condition, and surrounding context.
• Classify stall sources by origin: internal (arbitration, descriptor fetch latency, FIFO backpressure, etc.) vs. external (interconnect/AXI backpressure, roundtrip latency, etc.).
• HTML dashboard, built from the Parquet dataset, presenting per-sweep metrics, stall summaries, and automatically flagged issues.
  - Preliminary root-cause ranking of the top stall contributors across the sweep space.

The second goal is about producing a validated datapath and control-path dependency map (static cartography):

• Build a documented and validated map of the DMA data path and control path: pipeline stages, buffers, arbitration points, and the control dependencies that gate forward progress.
  - Represent dependencies as a graph linking each observed dynamic stall class to its structural origin.
• Use the cartography to explain why a given condition produces a stall, not just that it does.

The skills you bring:

• Master's studies in Electrical/Computer Engineering, Computer Science, or similar.
• Background in computer architecture, ASIC design, RTL HDL coding, and testbench design using SystemVerilog.
• Working knowledge of UVM and scripting (Tcl/Python) for EDA tools is preferred.
• Curiosity to turn throughput "symptoms" into clear, data-backed root causes - and the discipline to design controlled measurements.

Why join Ericsson?

At Ericsson, you'll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what's possible. To build solutions never seen before to some of the world's toughest problems. You'll be challenged, but you won't be alone. You'll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: Sweden (SE) || Stockholm

Req ID: 791605