Master Thesis: Configurable Access Policies for Hardware Priority Queue Schedulers
Ericsson ABSammanfattning
This master's thesis opportunity focuses on developing a diagnostic observability layer for hardware task schedulers in heterogeneous computing platforms. The role involves investigating access policy configurability for performance improvements while working with modeling and empirical evaluation. Candidates will engage in tasks related to computer architecture, ASIC design, and performance evaluation, primarily in Stockholm, Sweden.Det här erbjuder vi
Opportunity to work on innovative solutions to complex problems.Collaborative environment with diverse innovators.Encouragement of diverse and inclusive organization.
Ansök senast: Öppet tillsvidare
Publicerad: 2026-09-18
Beskrivning
Join our Team
About this opportunity:
Hardware task schedulers are key components in heterogeneous computing platforms such as network processors, baseband accelerators, and GPU command processors. A common pattern is the multi-queue priority scheduler: a hardware block managing many priority queues from which processing elements (PEs) request work items.
A central design question is the access policy - how a PE expresses which queues it is willing to receive work from. Most designs offer only two extremes: direct addressing (targeting a single queue) or fixed arbitration groups (selecting from a static, non-overlapping partition). These are efficient but rigid - fixed boundaries, uniform sizes, and no overlap - limiting the ability to express sharing, prioritization, or isolation requirements that modern dynamic workloads demand.
What you will do:
In this thesis you will investigate the design space between rigid static access modes and fully software-managed scheduling. The central question is:
"Given ASIC implementation constraints, which forms of access policy configurability yield meaningful performance or efficiency improvements, and at what cost?"
The work is anchored in modeling and empirical evaluation. Candidate policies are assessed both in terms of functional performance (throughput, arbitration latency, fairness) through high-level modeling, and in terms of implementation cost (silicon area, critical path timing, power) through RTL synthesis. The goal is actionable design guidance - characterizing when configurability helps, when it doesn't, and how much flexibility is "enough" for representative workload classes.
The skills you bring:
Why join Ericsson?
At Ericsson, you'll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what's possible. To build solutions never seen before to some of the world's toughest problems. You'll be challenged, but you won't be alone. You'll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
What happens once you apply?
Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: Sweden (SE) || Stockholm
Req ID: 791273
About this opportunity:
Hardware task schedulers are key components in heterogeneous computing platforms such as network processors, baseband accelerators, and GPU command processors. A common pattern is the multi-queue priority scheduler: a hardware block managing many priority queues from which processing elements (PEs) request work items.
A central design question is the access policy - how a PE expresses which queues it is willing to receive work from. Most designs offer only two extremes: direct addressing (targeting a single queue) or fixed arbitration groups (selecting from a static, non-overlapping partition). These are efficient but rigid - fixed boundaries, uniform sizes, and no overlap - limiting the ability to express sharing, prioritization, or isolation requirements that modern dynamic workloads demand.
What you will do:
In this thesis you will investigate the design space between rigid static access modes and fully software-managed scheduling. The central question is:
"Given ASIC implementation constraints, which forms of access policy configurability yield meaningful performance or efficiency improvements, and at what cost?"
The work is anchored in modeling and empirical evaluation. Candidate policies are assessed both in terms of functional performance (throughput, arbitration latency, fairness) through high-level modeling, and in terms of implementation cost (silicon area, critical path timing, power) through RTL synthesis. The goal is actionable design guidance - characterizing when configurability helps, when it doesn't, and how much flexibility is "enough" for representative workload classes.
The skills you bring:
- Master's student in Electrical/Computer Engineering, Computer Science, Embedded Systems, or similar.
- Background in Computer architecture, ASIC design, RTL HDL coding, scripting and modeling (Python/MATLAB).
- Interest and/or experience in AI is a plus.
Why join Ericsson?
At Ericsson, you'll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what's possible. To build solutions never seen before to some of the world's toughest problems. You'll be challenged, but you won't be alone. You'll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
What happens once you apply?
Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.
Primary country and city: Sweden (SE) || Stockholm
Req ID: 791273
Ansök till tjänsten
Master Thesis: Configurable Access Policies for Hardware Priority Queue Schedulers
OM FÖRETAGET
Ericsson AB
