ASIC Verification Engineer
Jamy InteractiveSammanfattning
This role focuses on hands-on verification of ASIC and SoC designs, requiring the development of test-benches and tests from scratch using SystemVerilog and UVM. The position involves maintaining existing tests and components, as well as developing and integrating Verification IPs. Candidates should have senior-level experience in ASIC/SoC verification and strong expertise in SystemVerilog and UVM.Beskrivning
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Hands-on ASIC Verification
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Develop verification test-benches from scratch for ASIC and SoC designs
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Develop tests from scratch using SystemVerilog and UVM
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Update and maintain existing tests for evolving designs
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Develop test-bench components from scratch (drivers, monitors, scoreboards, sequences)
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Update and extend existing test-bench components
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Develop Verification IPs (VIPs) from scratch
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Maintain and enhance existing VIPs
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Integrate third-party VIPs into the verification environment
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Implement SystemVerilog Assertions (SVA)
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Implement functional and code coverage
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Analyze coverage results, identify gaps, and create tests to achieve coverage closure
Required Skills & Qualifications
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Senior-level experience in ASIC/SoC verification
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Strong expertise in SystemVerilog and UVM
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ASIC Verification Engineer
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