ASIC Verification Engineer
Jamy InteractivesSammanfattning
This role involves developing and maintaining verification plans and environments for ASIC/SoC designs using SystemVerilog and UVM. The position requires collaboration with various engineering teams to ensure functionality and performance through rigorous testing and debugging. The work is likely to be conducted in a technical environment focused on pre-silicon verification and may include post-silicon activities.Beskrivning
Key Responsibilities
Develop comprehensive verification plans based on design specifications and requirements.
Develop and maintain SystemVerilog/UVM-based verification environments.
Create reusable testbenches, test cases, sequences, drivers, monitors, scoreboards, and functional coverage models.
Develop directed and constrained-random tests to validate ASIC/SoC functionality.
Write and maintain SystemVerilog Assertions (SVA) for protocol and functional verification.
Perform simulation, regression testing, coverage analysis, and failure debug.
Analyze code coverage, functional coverage, assertion coverage, and verification metrics.
Debug RTL, testbench, and simulation failures using industry-standard EDA tools.
Verify standard and proprietary interfaces/protocols such as AXI, AHB, APB, PCIe, USB, DDR, or other relevant protocols.
Collaborate closely with RTL designers, architects, firmware engineers, and physical design teams to identify and resolve issues.
Track bugs, document verification results, and contribute to verification sign-off.
Improve verification infrastructure, automation, and regression flows.
Support pre-silicon verification and, where applicable, post-silicon debug activities.
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ASIC Verification Engineer
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