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Master Thesis: ASIC FPGA code converting

Ericsson AB

Sammanfattning

This opportunity involves developing a Python-based toolchain for converting ASIC RTL to FPGA RTL and vice versa, addressing the challenges of vendor-specific differences in design implementation. The role is based in Stockholm, Sweden, and offers a chance to work on innovative solutions within a diverse team at Ericsson, focusing on enhancing RTL reuse across platforms.
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Det här erbjuder vi

Opportunity to work on innovative solutions to complex problems.Collaborative environment with a diverse team of innovators.Encouragement of diverse and inclusive organizational culture.

Stockholm

Ansök senast: Öppet tillsvidare
Publicerad: 2026-09-15

Beskrivning

Join our Team

About this opportunity:

ASIC and FPGA development both use RTL as the design source. However, implementation relies on different hard IPs and primitives that vary not only between ASIC and FPGA, but also across vendors. These differences mean RTL cannot be directly reused across targets even if the syntax is the same. This thesis addresses that gap by developing a conversion toolchain that automatically maps primitives and IP instantiations and handles vendor-specific differences, enabling RTL reuse between ASIC and FPGA flows.

What you will do:

  • Develop a Python-based toolchain (with a simple GUI) to convert ASIC RTL to FPGA RTL and vice versa
  • Automatically replace primitives and IP instantiations during conversion, accounting for vendor-specific constructs
  • Investigate and compare current research and methods for RTL conversion
  • Identify major implementation/synthesis tool vendors (e.g., Synopsys, AMD/Xilinx, Cadence, Intel) and document key differences relevant to conversion
  • Use the developed toolchain to convert an example ASIC design to FPGA RTL and run place-and-route to closure (no errors)
  • Conclude with a results presentation to the Ericsson Research team


The skills you bring:

  • Master's studies in Electrical Engineering, Computer Science, Computer Engineering, or similar
  • Background in Python and RTL code development
  • Familiarity with digital design (SystemVerilog/Verilog/VHDL), FPGA/ASIC flows, and vendor tools (e.g., Synopsys, Cadence, AMD/Xilinx, Intel) is meriting
  • Understanding of EDA tool differences and IP/primitives mapping is a plus


Why join Ericsson?

At Ericsson, you'll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what's possible. To build solutions never seen before to some of the world's toughest problems. You'll be challenged, but you won't be alone. You'll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.

What happens once you apply?

Click Here to find all you need to know about what our typical hiring process looks like.Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more.

Primary country and city: Sweden (SE) || Stockholm

Req ID: 790480

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Master Thesis: ASIC FPGA code converting

Denna arbetsplats har annonserats på Ericsson-tjänsten den 2026-09-15 och publicerades av Ericsson.
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