ASIC Verification Engineer

Om jobbet

About the job

As our Stockholm office keeps growing, we are now looking to hire more world-class engineers focused on expertise in ASIC Verification and development. You will have the chance to work closely with your colleagues and manager to develop your future skill set.

Your role

You will be working with a variety of tasks including testbench development and IP / SoC design verification in ASIC / FPGA projects.

Take full responsibility for verification of a design, being block or sub-system

Define and implement UVM based test environments

Break-down Requirements and create Verification Specifications and defining test cases

Develop, run and debug test cases

Generate documentation

Develop test cases for IPs and SoCs

Test environment and design debugging

Creation of Scoreboards

Refinement of assertions and coverage

Creation of relevant documentation

The verification mostly uses constrained random methodology. Dedicated test vectors and assertions are also used.

Your profile

Requirements:

10+ years of experience in a relevant area of verification

Advanced user of System Verilog

Advanced user of UVM tools and methodology for IP verification

Significant experience in assertions, scoreboards and coverage refinement

Excellent programming skills (SV, VHDL)

Good scripting skills using eg Python, TCL and / or Perl

Meritorious:

An Master's degree in electronics or the equivalent level of education

Experience in system level verification

Knowledge about formal verification

Knowledge in programming C, C++ and System C